AgentsThe story, in brief

Cadence Expands ChipStack AI to Generate and Optimize RTL

Cadence's ChipStack AI agent now writes RTL from natural language—automating the spec-to-silicon workflow that has bottlenecked chip design for decades.

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AI agents and the coordination of work.AI illustration by KeyNews
The KeyNews take

Why it matters

An autonomous agent handling front-end digital design (spec-to-RTL generation, analysis, refinement) represents a material shift in how chips get designed. This is not a model release or a tool feature—it's autonomous multi-step engineering work moving into production workflows at a major EDA vendor.

The key facts

6 to know
  1. Cadence ChipStack AI Super Agent expanded with RTL generation and optimization capability

  2. Handles power, performance, and area (PPA)-driven spec-to-RTL generation from natural language prompts

  3. Includes RTL analysis and refinement in the agentic workflow

  4. Positioned as industry's first agentic workflow for front-end design and verification

  5. Announced September 22, 2026

  6. Agent operates autonomously across multiple design stages without human intervention between steps

Go to the source

EnterpriseAIhpcwire.com

Publisher excerpt: SAN JOSE, Calif., Sept. 22, 2026 — Cadence today introduced a new agent for Cadence ChipStack AI Super Agent that automates front‑end digital design and verification—covering power, performance and area (PPA)-driven spec‑to‑RTL generation, RTL analysis, and refinement; all from natural language…
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