Cadence Expands ChipStack AI to Generate and Optimize RTL
Cadence's ChipStack AI agent now writes RTL from natural language—automating the spec-to-silicon workflow that has bottlenecked chip design for decades.
Why it matters
An autonomous agent handling front-end digital design (spec-to-RTL generation, analysis, refinement) represents a material shift in how chips get designed. This is not a model release or a tool feature—it's autonomous multi-step engineering work moving into production workflows at a major EDA vendor.
The key facts
6 to knowCadence ChipStack AI Super Agent expanded with RTL generation and optimization capability
Handles power, performance, and area (PPA)-driven spec-to-RTL generation from natural language prompts
Includes RTL analysis and refinement in the agentic workflow
Positioned as industry's first agentic workflow for front-end design and verification
Announced September 22, 2026
Agent operates autonomously across multiple design stages without human intervention between steps
Go to the source
EnterpriseAIhpcwire.com
Publisher excerpt: SAN JOSE, Calif., Sept. 22, 2026 — Cadence today introduced a new agent for Cadence ChipStack AI Super Agent that automates front‑end digital design and verification—covering power, performance and area (PPA)-driven spec‑to‑RTL generation, RTL analysis, and refinement; all from natural language…