Cadence Expands TSMC Partnership for AI and HPC Chip Design
Cadence certified on TSMC A14. Wafer-scale 3D-IC for hundreds of chiplets. The design-software layer just got real for next-gen AI silicon.
Why it matters
Cadence's A14 certification and silicon-proven IP on N3P/N2P, combined with wafer-scale 3D-IC capabilities and agentic AI design flows, materially accelerates the tooling readiness for the next generation of AI/HPC chip design. This is the plumbing practitioners need to ship.
The key facts
9 to knowCadence achieved TSMC A14 process certification
Silicon-proven IP available on TSMC N3P and N2P nodes
Wafer-scale 3D-IC support for hundreds of chiplets
Agentic AI design flows integrated into partnership
Expanded strategic partnership between Cadence and TSMC
Cadence achieved tool certification for TSMC A14 process
Silicon-proven IP on TSMC N3P and N2P nodes
Agentic AI flows integrated into design toolchain
Partnership announced September 24, 2026
Go to the source
EnterpriseAIhpcwire.com
Publisher excerpt: Expanded partnership spans TSMC A14 certification, silicon-proven IP on TSMC N3P/N2P, wafer-scale 3D-IC for hundreds of chiplets, and agentic AI flows SAN JOSE, Calif., Sept. 24, 2026 — Cadence has announced an expanded partnership with TSMC to deliver advanced capabilities for AI and HPC…