ChipsJuly 24, 2026via SiliconAngle
Synopsys targets physical AI complexity with co-design and agentic chip workflows
Why it matters
As transistor counts explode toward hundreds of billions, traditional EDA workflows are becoming obsolete. Synopsys is deploying agentic AI and co-design methodologies to keep pace with physical AI demands — a critical bottleneck for hyperscale compute infrastructure.
Key signals
- Chip design complexity outpacing traditional engineering methods
- Hundreds of billions of transistors per component
- Focus on autonomous vehicles and hyperscale data centers
- Synopsys deploying agentic chip workflows
- Co-design approach to reduce design iteration cycles
- Physical AI as emerging design paradigm
The hook
Chip design just hit a complexity wall. Synopsys is using AI agents to solve it.
The rapid evolution of intelligent software-defined systems is pushing chip design into a new era of physical AI, one where chip design complexity is outpacing traditional engineering methods. Manufacturers are racing to cram hundreds of billions of transistors into components that power everything …